TTTC: DFT 2012 Call for Participation - Discount Deadline September 16th!

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Registration -- Advance Program -- More Information -- Committees

Scope

DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field.

All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.

The symposium is held yearly, around the world, and this year will be located in Austin, Texas, U.S.A.

Key Dates

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Advance Discount Registration Deadline: September 16th, 2012!

The Venue

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The conference will be located at the University of Texas at Austin, and the technical sessions will be hosted in the Thompson Conference Center.

Maps and directions to reach the venue can be found here.

There is no preferred hotel where to stay among the several in the area.

Registration

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Conference registration now open on the website.

Advance Program

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Preliminary technical program now available link.

More Information

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For more information on general aspects and location matters, please contact the general co-chairs:

Prashant D. Joshi prashant.d.joshi@intel.com
Massimo Violante massimo.violante@polito.it

For more information on general aspects and location matters, please contact the technical program co-chairs:

Jie Han jhan8@ualberta.ca
Ramesh Karri rkarri@poly.ed

Committees

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General co-chairs
Prashant D. Joshi (Intel,USA)
Massimo Violante (Politecnico di Torino, Italy)

Program co-chairs
Jie Han (University of Alberta, Canada)
Ramesh Karri (Polytechnic Institute of NYU, U.S.A)

Publicity chair
Antonio Miele (Politecnico di Milano, Italy)

Publication chair
Qiaoyan Yu (University of New Hampshire, U.S.A.)
Technical Program Committee

P. Ampadu, University of Rochester
C. Bolchini, Politecnico di Milano
S. Chakravarty, LSI Logic
G. Chapman, Simon Fraser University
L. Chen, University of Saskatchewan
Y. Choi, Hongik University
A. Daniel, Intel
L. Dilillo, LIRMM
B. Eklow, CISCO
M. Favalli, University of Ferrara
M. Fukushi, Tohoku University
D. Gizopoulos, University of Athens
S. Hamdioui, Delft University of Technology
C. Huang, Nat'l Tsing Hua U.
N. Jha, Princeton
W. Jone, University of Cincinnati
Y. Kim, Northeastern University
I. Koren, UMASS Amherst
R. Leveugle, TIMA labs
X. Li, Chinese Academy of Science
H. Li, Chinese Academy of Science
F. Lombardi, Northeastern University
Y. Makris, UT Dallas
C. Metra, University of Bologna
A. Miele, Politecnico di Milano
K. Namba, Chiba University
N. Nicolici, McMaster University
M. Ottavi, University of Rome "Tor Vergata"
N. Park, Oklahoma State University
A. Paschalis, University of Athens
Z. Peng, Linkoping University
W. Pleskacz, Warsaw U.T.
S. Pontarelli, University of Rome "Tor Vergata"
M. Rebaudengo, Politecnico di Torino
S. Reddy, University of Iowa
F. Salice, Politecnico di Milano
D. Sciuto, Politecnico di Milano
O. Sinanoglu, New York University
M. Tehranipoor, University of Connecticut
J. Teixeira, INESC-ID Lisboa
C. Thibeault, Ecole de Tech.
N. Touba, University of Texas at Austin
S. Tragoudas, Southern Illinois Univ. Carbondale
R. Velazco, TIMA labs
D. Xiang, Tsinghua University
Q. Xu, Chinese University of Hong Kong
Q. Yu, University of New Hampshire
L. Wang, University of Connecticut
X. Wen, Kyushu Institute of Technology

For more information, visit us on the web at: http://www.dfts.org/

The IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).